1. Field of the Invention
The present invention generally relates to analog-to-digital converters (ADCs). More specifically, the present invention provides an improved front-end ADC pipeline sampling technique to accommodate high frequency analog input signals.
2. Background Art
Pipeline ADCs are often used to generate multiple bit digital representations of analog signals. Each stage of a pipeline ADC resolves a few bits of the overall multiple bit digital representation. By combining the outputs of each stage of the pipeline ADC, a high resolution, multiple bit representation is formed.
Pipeline ADC stages generally include a flash comparator and a residual generator. The flash comparator generates the output bits for the ADC stage. The residual generator generates an error signal that is passed to the next ADC stage to further refine the representation of the analog input signal.
To ensure proper operation of the ADC stage, the flash comparator and residual generator should operate on substantially the same sample of the analog input signal. To meet this requirement, many conventional ADC stage designs use a front-end sample-and-hold (S/H) circuit. Other conventional ADC stage designs require the sampling networks of the residual generator and flash comparator to be precisely matched. Both prior art designs can suffer from a number of drawbacks including high noise introduction and high power requirements or they can strain the operational capabilities of the residual generator. Overall, both designs may limit the frequency range of the analog input signal that can be received and processed by the ADC stage.
Accordingly, there is a need for an ADC stage and sampling technique that obviates the need for a front-end S/H circuit while still supporting high frequency analog input signals.